Japanese Patent Application Laid-Open Publication No. H03-218658 (Patent Document 1) has disclosed a multilayer lead frame structure in which an inner lead and a metal plane are adhered to each other via an insulating layer and in which a through hole is formed in one or both of the sides sandwiching a wire-bonding region of the metal plane.
Japanese Patent Application Laid-Open Publication No. 2002-76228 (Patent Document 2) has disclosed a semiconductor device in which a semiconductor chip mounted on a die pad is electrically connected to the die pad via wires. In Patent Document 2, the die pad has a silver plated film formed over a portion to which the wires are connected.
Japanese Patent Application Laid-Open Publication No. 2002-261187 (Patent Document 3) has disclosed a semiconductor device in which a semiconductor chip mounted on a die pad is electrically connected to the die pad via wires. In Patent Document 3, the die pad has a plated film formed over a portion to which the wires are connected and a trench or a slit formed between the plated film and the semiconductor chip.